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| - 1 - k8a2815et(b)e rev. 1.0, nov. 2010 samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference pur poses only. all info rmation discussed herein is provided on an "as is" bas is, without warranties of any kind. this document and all information discussed herein re main the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, tradem ark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where pr oduct failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered tradem arks belong to their respective owners. ? 2009 samsung electronics co., ltd. all rights reserved. 128mb e-die nor flash 8m x16, sync burst, page mode, multi bank 1.7v to 1.95v datasheet
- 2 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e revision history revision no. history draft date remark editor 0.0 - initial draft. jul. 2010 target - 0.5 - preliminary datasheet. 28, oct. 2010 preliminary - 1.0 - specification is fi nalized. 23, nov. 2010 final - - 3 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e 128mb e-die nor flash 1 1.0 features................................................................................................................... .............................................. 4 2.0 general description ........................................................................................................ ................................. 4 3.0 pin description ............................................................................................................ ........................................ 5 4.0 functional block diagram ................................................................................................ ........................... 5 5.0 ordering information ....................................................................................................... ............................... 6 6.0 product introduction....................................................................................................... ............................... 8 7.0 command definitions ........................................................................................................ ................................. 9 7.1 command definitions ................ .............. .............. .............. .............. ............ ........... ......... ....................................... 9 8.0 device operation ........................................................................................................... ..................................... 11 8.1 read mode .................................................................................................................. ............................................ 11 8.2 asynchronous read mode ............. .............. .............. .............. .............. ........... ........... .......... ................................. 11 8.3 synchronous (burst) read mode ... .............. .............. .............. .............. .............. ........... .......... .............................. 12 8.4 output driver setting ...................................................................................................... ......................................... 12 8.5 programmable wait state .................................................................................................... ................................... 13 8.6 set burst mode configuration re gister ...................................................................................... ............................. 13 8.6.1 extended configuration register (option : k8a2615et(b)e only) ........... .............. .............. ............ ......... ........ 13 8.7 programmable wait state configuration ...................................................................................... ........................... 13 8.8 burst read mode setting .................................................................................................... .................................... 14 8.9 rdy configuration.......................................................................................................... ......................................... 14 8.10 autoselect mode........................................................................................................... ......................................... 14 8.11 standby mode .............................................................................................................. ......................................... 14 8.12 automatic sleep mode ..................................... ................................................................. .................................... 14 8.13 output disable mode....................................................................................................... ...................................... 14 8.14 block protection & unprotection ........................................................................................... ................................. 15 8.15 hardware reset........ .................................................................................................... ......................................... 15 8.16 software reset ............................................................................................................ .......................................... 15 8.17 program................................................................................................................... .............................................. 15 8.18 accelerated program operation ............................................................................................. ............................... 16 8.19 unlock bypass............................................................................................................. .......................................... 16 8.20 chip erase ................................................................................................................ ............................................. 16 8.21 block erase ............................................................................................................... ............................................ 16 8.22 erase suspend / resume.................................................................................................... .................................. 17 8.23 program suspend / resume .................................................................................................. ............................... 17 8.24 read while write operation ................................................................................................ .................................. 17 8.25 otp block region .......................................................................................................... ....................................... 17 8.26 write pulse ?glitch? protection ........................................................................................... ................................... 17 8.27 low vcc write inhibit ..................................................................................................... ...................................... 18 8.28 logical inhibit........................................................................................................... .............................................. 18 8.29 power-up protection ....................................................................................................... ....................................... 18 8.30 flash memory status flags ................................................................................................. ..................... 18 9.0 common flash memory interface .............................................................................................. .................. 20 10.0 absolute maximum ratings ............................................................... ...................................................... 22 11.0 recommended operating condit ions ( voltage reference to gnd ) ..................................................... 22 12.0 dc characteristics ............................................................... ............................................................... ..... 22 13.0 capacitance(ta = 25 c, vcc = 1.8v, f = 1.0mhz) ............................................................... ........................ 24 14.0 ac test condition ............................................................... ............................................................... ........ 24 15.0 ac characteristics ........................................................................................................ .................................. 24 15.1 synchronous/burst read ............................................................... ............................................................... ...24 15.2 asynchronous read ............................................................... ............................................................... ..........27 15.3 hardware reset(reset) ............................................................... ............................................................... ..29 15.4 erase/program operation ............................................................... ............................................................... ..30 16.0 flash erase/program performance ............................................................... .................................... 30 17.0 crossing of first word boundary in burst read mode ................................................................... 36 - 4 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e 128m bit (8m x16) sync bu rst / page mode / mult i bank nor flash memory 1.0 features ? single voltage, 1.7v to 1.95v for read and write operations ? organization - 8,386,108 x 16 bit (word mode only) ? read while program/erase operation ? multiple bank architecture - 16 banks (8mb partition) ? otp block : extra 256word block ? read access time (@ c l =30pf) - asynchronous random access time : 70ns - synchronous random access time : 70ns - burst access time : 14.5ns (54mhz) / 11ns (66mhz) / 9ns (83mhz) / 7ns (108mhz) ? page mode operation 8-words page access allows fast asychronous read page read access time : 20ns ? burst length : - continuous linear burst - linear burst : 8-word & 16-word with wrap ? block architecture - eight 4kword blocks and two hundreds fifty-five 32kword blocks - bank 0 contains eight 4 kword blocks and fifteen 32kword blocks - bank 1 ~ bank 15 contain two hundred forty 32kword blocks ? reduce program time using the v pp ? support single & quad word accelerate program ? power consumption (typical value, c l =30pf) - async/sync burst access current : 24ma - program/erase current : 15ma - read while program/erase current : 40ma - standby mode/auto sleep mode :15ua ? block protection/unprotection - using the software command sequence - last two boot blocks are protected by wp =v il - all blocks are protected by v pp =v il ? handshaking feature - provides host system with minimum latency by monitoring rdy ? erase suspend/resume ? program suspend/resume ? unlock bypass program/erase ? enhanced block protection (option) ? extended configuration register for synchronous read operation (option) ? hardware reset (reset ) ? data polling and toggle bits - provides a software method of detecting the status of program or erase completion ? endurance 100k program/erase cycles minimum ? extended temperature : -25 c ~ 85 c ? support common flash memory interface ? low vcc write inhibit ? package : tbd 2.0 general description the k8a2815e featuring single 1.8v power supply is a 128mbit synchro- nous burst multi bank flash memory organized as 8mx16. the memory architecture of the device is designed to divide its memory arrays into 263 blocks with independent hardware protec tion. this block architecture pro- vides highly flexible erase and program capability. the k8a2815e nor flash consists of sixteen banks. this device is capable of reading data from one bank while programming or erasing in the other bank. regarding read access time, the k8a2815e provides an 14.5ns burst access time and an 70ns initial access time at 54mhz. at 66mhz, the k8a2815e provides an 11ns burst ac cess time and 70ns initial access time. at 83mhz, the k8a2815e provides an 9ns burst access time and 70ns ini- tial access time. at 108mhz, the k8a 2815e provides an 7ns burst access time and 70ns initial access time. t he device performs a program operation in units of 16 bits (word) and an erase operation in units of a block. single or multiple blocks can be erased. t he block erase operation is completed within typically 0.7sec. the device r equires 15ma as program/erase current in the extended temperature ranges. the k8a2815e nor flash memory is created by using samsung's advanced cmos process technology. - 5 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e 3.0 pin description 4.0 functional block diagram vcc vss ce oe we wp reset rdy a0~a22 dq15 interface & bank control x dec y dec latch & control latch & control dec x y dec erase control program control high voltage gen. bank 1 cell array bank 0 address bank 1 address bank 0 cell array avd dq0~ x dec y dec latch & control bank 15 cell array block inform vpp bank 15 address clk i/o pin name pin function a0 - a22 address inputs dq0 - dq15 data input/output ce chip enable oe output enable reset hardware reset pin vpp accelerates programming we write enable wp hardware write protection input clk clock rdy ready output avd address valid input vcc power supply v ss ground - 6 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e 5.0 ordering information note : density : (1) 26 : 128mb with the sync mrs option (extended configuration register) (2) 28 : 128mb with no option [table 1] product line-up [table 2] k8a2815e device bank divisions k8a2815e mode speed option 7b (54mhz) 7c (66mhz) 7d (83mhz) 7e (108mhz) v cc =1.7v- 1.95v synchronous/burst max. initial access time (t iaa, ns) 70 70 70 70 max. burst access time (t ba, ns) 14.5 11 9 7 asynchronous max. access time (t aa, ns) 70 70 70 70 max. page access time (t pa, ns) 20 20 20 20 max. ce access time (t ce, ns) 70 70 70 70 max. oe access time (t oe, ns) 20 20 20 20 bank 0 bank 1 ~ bank 15 mbit block sizes mbit block sizes 8 mbit eight 4kwords, fifteen 32kwords 120 mbit two hundred forty 32kwords k8 a 28 15 e t(b) e - s e 7e samsung nor flash memory device type a : sync burst(demuxed) density (note) 26 : 128mbits * (1) 28 : 128mbits * (2) operating temperature range c :commercial temp. (0 c to 70 c) e :extended temp. (-25 c to 85 c) block architecture t : top boot block, b : bottom boot block version e : 6th generation access time 7e : refer to table 1 operating voltage range e : 1.7 v to 1.95v package f : fbga, d : fbga(lead free) s : fbga(lead free, osp) organization 15 : x16 organization - 7 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e [table 3] K8A2815ETE device bank divisions [table 4] k8a2815ebe device bank divisions bank quantity of blocks block size 0 8 4 kwords 15 32 kwords 1 16 32 kwords 2 16 32 kwords 3 16 32 kwords 4 16 32 kwords 5 16 32 kwords 6 16 32 kwords 7 16 32 kwords 8 16 32 kwords 9 16 32 kwords 10 16 32 kwords 11 16 32 kwords 12 16 32 kwords 13 16 32 kwords 14 16 32 kwords 15 16 32 kwords bank quantity of blocks block size 15 16 32 kwords 14 16 32 kwords 13 16 32 kwords 12 16 32 kwords 11 16 32 kwords 10 16 32 kwords 9 16 32 kwords 8 16 32 kwords 7 16 32 kwords 6 16 32 kwords 5 16 32 kwords 4 16 32 kwords 3 16 32 kwords 2 16 32 kwords 1 16 32 kwords 0 15 32 kwords 8 4 kwords - 8 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e 6.0 product introduction the k8a2815e is a 128mbit (134,217,728 bits) nor-type burst flash memory . the device features 1.8v single voltage power supply operating within the range of 1.7v to 1.95v. the device is programmed by using the c hannel hot electron (che) injecti on mechanism which is used to p rogram eproms. the device is erased electrical ly by using fowler-nordheim t unneling mechanism. to provide highl y flexible erase and program ca pability, the device adopts a block memory architecture that divides its memory ar ray into 263 blocks (32-kword x 255 , 4-kword x 8). programming i s done in units of 16 bits (word). all bits of data in one or multiple blocks can be eras ed when the device executes the erase operation. to prevent the d evice from accidental eras- ing or over-writing the programmed data, 263 memory blocks can be hardware protected. regarding read access time, at 54mhz, the k8a2815e pro- vides a burst access of 14.5ns with initia l access times of 70ns at 30pf. at 66mhz, t he k8a2815e provides a burst access of 11n s with initial access times of 70ns at 30pf. at 83mhz, the k8a2815e provides a burst access of 9ns with initial access ti mes of 70ns at 30pf. at 108mhz, th e k8a2815e provides a burst access of 9ns with initial access times of 70ns at 30pf. the command set of k8a2815e is compatible with standard flash de vices. the device uses chip enable (ce ), write enable (we ), address valid(avd ) and output enable (oe ) to control asynchronous read and write operation. for burst opera- tions, the device additionally requires ready (rdy) and clock (clk). device operations are executed by selective command codes. the command codes to be combined with addresses and data are sequentially writt en to the command registers using microprocessor write timing. the command codes serve as inputs to an internal state machine which controls the program /erase circuitry. register cont ents also internally latch addr esses and data necessary to execute the program and erase operations. the k8a2815e is implemented with internal program/erase routines to execute the progr am/erase opera- tions. the internal program/erase routines are invoked by pr ogram/erase command sequences. the internal program routine automat ically programs and verifies data at specified addresses. the internal erase routine automatically pre- programs the memory cell which is not pr ogrammed and then exe- cutes the erase operation. the k8a2815e has means to indicate t he status of completion of program/erase operations. the status can be indicated via data polling of dq7, or the toggle bit (dq6). once the operati ons have been completed, the device automatically resets itself t o the read mode. the device requires 24ma burst read current and 15 ma for program/erase operations. [table 5] device bus operations note : l=vil (low), h=vih (high), x=don?t care. operation ce oe we a0-22 dq0-15 reset clk avd asynchronous read operation l l h add in i/o h l l write l h add in i/o h l x standby hxxxhigh-zhxx hardware reset xxxxhigh-zlxx load initial burst address l h h add in x h burst read operation l l h x burst d out hh terminate burst read cycle hxxxhigh-zhxx terminate burst read cycle via reset xxxxhigh-zlxx terminate current burst read cycle and start new burst read cycle l h h add in i/o h - 9 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e 7.0 command definitions 7.1 command definitions the k8a2815e operates by selecting and executing its operational modes. each operational mode has its own command set. in order to select a certain mode, a proper command with specific address and data sequences mu st be written into the command register. writing incorrect in formation which include address and data or writing an improper command will reset the device to the read mode. the defined valid register comm and sequences are stated in table 6. [table 6] command sequences command definitions cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle asynchronous read add 1 r a data rd reset 5) add 1 xxxh data f0h autoselect manufacturer id 6) add 4 555h 2aah (da)555h (da)x00h data aah 55h 90h ech autoselect device id 6) add 4 555h 2aah (da)555h (da)x01h data aah 55h 90h note6 autoselect block protection verify 7) add 4 555h 2aah (ba)555h (ba)x02h data aah 55h 90h 00h / 01h autoselect handshaking 6), 8) add 4 555h 2aah (da)555h (da)x03h d a t a a a h 5 5 h 9 0 h 0 h / 1 h program add 4 555h 2aah 555h pa data aah 55h a0h pd unlock bypass add 3 555h 2aah 555h data aah 55h 20h unlock bypass program 9) add 2 xxx pa data a0h pd unlock bypass block erase 9) add 2 xxx ba data 80h 30h unlock bypass chip erase 9) add 2 xxxh xxxh data 80h 10h unlock bypass reset add 2 xxxh xxxh data 90h 00h quadruple word accelerated program 16) add 5 xxxh pa1 pa2 pa3 pa4 data a5h pd1 pd2 pd3 pd4 chip erase add 6 555h 2aah 555h 555h 2aah 555h data aah 55h 80h aah 55h 10h block erase add 6 555h 2aah 555h 555h 2aah ba data aah 55h 80h aah 55h 30h erase suspend 10) add 1 (da)xxxh data b0h erase resume 11) add 1 (da)xxxh data 30h program suspend 12) add 1 (da)xxxh data b0h program resume 11) add 1 (da)xxxh data 30h - 10 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e note : 1) ra : read address , pa : program address, rd : read data, pd : program data , ba : block address (a22 ~ a12) da : bank address (a22 ~ a19) , abp : address of the block to be protected or unprotected, cr : configuration register sett ing 2) the 4th cycle data of autoselect mode and rd are output data. the others are input data. 3) data bits dq15?dq8 are don?t care in command sequences, except for rd, pd and device id. 4) unless otherwise noted, address bits a22?a11 are don?t cares. 5) the reset command is required to return to read mode. if a bank entered the autoselect mo de during the erase suspend mode, writing the reset command returns that bank to the era se suspend mode. if a bank entered the autoselect mode during the program su spend mode, writing the reset command returns that bank to the p rogram suspend mode. if dq5 goes high during the program or erase operation, writ ing the reset command returns that bank to read mode or erase s uspend mode if that bank was in erase suspend mode. 6) the 3rd and 4th cycle bank address of autoselect mode must be same. device id data : "2402h" for top boot bl ock device, "2403h" for bottom boot block device 7) 00h for an unprotected block and 01h for a protected block. for otp block protection verify, 3rd command cycle is (da)555h/90h. da(bank address) should be invoked instead of ba(block addr ess). 8) 0h for handshaking, 1h for non-handshaking 9) the unlock bypass command sequence is required prior to this command sequence. 10) the system may read and program in non-erasing blocks when in the erase suspend mode. the system may enter the autos elect mode when in the erase suspend mode. the erase suspend command is valid only duri ng a block erase operation, and requires the bank address. 11) the erase/program resume command is valid only during t he erase/program suspend mode, and requires the bank address. 12) this mode is used only to enable data read by suspending the program operation. 13) set block address(ba) as either a6 = vih, a1 = vih and a0 = vil for unprotected or a6 = vil, a1 = vih and a0 = vil for prot ected. 14) command is valid when the device is in read mode or autoselect mode. 15) see "set burst mode configuration register" for details. on the third cycle, the data should be "c0h" and address bits a20-a12 set the code to be latched. 16) quadruple word accelerated program is invoked only at vpp=v id ,vpp setup is required prior to this command sequence. pa1, pa2, pa3, pa4 have the same a22~a2 address. 17) cr is xxxa12 + 555h in extended configuration register command definitions cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle block protection/unprotection 13) add 3 xxx xxx abp data 60h 60h 60h cfi query 14) add 1 (da)x55h data 98h set burst mode configuration register 15) add 3 555h 2aah (cr)555h data aah 55h c0h set extended configuration register 17) add 3 555h 2aah (cr)555h data aah 55h c5h enter otp block region addr 3 555h 2aah 555h data aah 55h 70h exit otp block region addr 4 555h 2aah 555h xxx data aah 55h 75h 00h - 11 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e 8.0 device operation to write a command or command sequence (which includes programming data to the device and erasing blocks of memory), the system must drive clk, we and ce to v il and oe to v ih when providing address or data. the device provide the unl ock bypass mode to save its program time for program oper- ation. unlike the standard program command sequence which is compris ed of four bus cycles, only two program cycles are require d to program a word in the unlock bypass mode. one block, mult iple blocks, or the entire device can be er ased. table 3 indicates the address space that each block occupies. the device?s address space is divided into si xteen banks: bank 0 contains the boot/parameter blocks, and the other banks(from b ank 1 to 15) consist of uniform blocks. a ?bank address? is the addre ss bits required to uniquely select a bank. similarly, a ?block address? is the ad dress bits required to uniquely select a block. i cc2 in the dc characteristics table represents the active current specification for the write mode. the ac characteristics section contains timing specification tables and ti ming diagrams for write operations. 8.1 read mode the device automatically enters to asynchronous read mode after device power-up. no commands are required to retrieve data in a synchronous mode. after completing an internal program/erase routine, each bank is ready to read array data. the reset command is required to ret urn a bank to the read(or erase-suspend-read)mode if dq5 goes high duri ng an active program/erase operation, or if the bank is in the autoselect mode. the synchronous(burst) mode will automatically start on the last rising edge of the clk input while avd is held low. that means device enters burst read mode from asynchronous read mode to burst read mode using clk and avd signal. when the burst read is finished(or terminated), the device return to asynchronous read mode automatically. (1) k8a26(29)15et(b)e : sync mrs option (extended configuration register) the synchronous(burst) mode will automatically start on the rising edge of the clk input while avd is held low after extended mode register setting to a12=1. if several clks exist in avd low, the last rising edge is valid clk. (2) k8a27(28)15et(b)e : no sync mrs option the synchronous(burst) mode will automatically start on the rising edge of the clk input while avd is held low. if several clks exist in avd low, the last rising edge is valid clk. 8.2 asynchronous read mode for the asynchronous read mode a valid address should be asserted on a0-a22, while driving avd and ce to v il . we should remain at v ih . the data will appear on dq0-dq15. since the memory array is divided into si xteen banks, each bank remains enabled for read access until the c ommand register con- tents are altered. address access time (t aa ) is equal to the delay from valid addresses to valid output data. the chip enable access time(t ce ) is the delay from the falling edge of ce to valid data at the outputs. the output enable access time(t oe ) is the delay from the falling edge of oe to valid data at the output. to prevent the memory content from spurious alteri ng during power transition, the initial state machine is set for reading array data upon device power-up, or after a hardware reset. 8-words page mode is supported for fast asyn chronous read. after address access time(t aa ), eight data words are loaded into an internal page buffer. a0~a2 bits determine which page word is output during a read operation. a3~a22 and avd must be stable throughout the page read access. figure 10 shows the asynchronous page read mode timing. - 12 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e 8.3 synchronous (burst) read mode the device is capable of continuous linear burst operation and linear burst operation of a preset length. for the burst mode, t he system should determine how many clock cycles are desired for the initial word(t iacc ) of each burst access and what mode of burst operation is desired using "burst mode config- uration register" command sequences. see "set burst mode configur ation" for further details. the status data also can be read d uring burst read mode by using avd signal with a bank address. to initiate the synchronous read again, a new address and avd pulse is needed after the host has completed status reads or the device has comp leted the program or erase operation. continuous linear burst read (1) k8a26(29)15et(b)e : sync mrs option (extended configuration register) the synchronous(burst) mode will automatically start on the rising edge of the clk input while avd is held low after extended mode register setting to a12=1. if several clks exist in avd low, the last rising edge is valid clk. (2) k8a27(28)15et(b)e : no sync mrs option the synchronous(burst) mode will automatically start on the rising edge of the clk input while avd is held low. if several clks exist in avd low, the last rising edge is valid clk. note that the device is enabled for asynchronous mode w hen it first powers up. the initial word is output t iaa after the rising edge of the last clk cycle. subsequent words are output t ba after the rising edge of each successive clock cycle, which automa tically increments the internal address counter. note that the device has internal address boundary that occurs every 16 words. when the device is crossing the first word boundary, additional clo ck cycles are needed before data appears for the next address. the number of additi onal clock cycle can varies fr om zero to seven cycles, and the exact number of additional clock cycle depends on t he starting address of burst read.(refer to fi gure 18) the rdy output indicates this conditi on to the system by pulsing low. the device will continue to output sequential burst dat a, wrapping around to address 000000h after it reaches the highest addressable memory loca- tion until the system asserts ce high, reset low or avd low in conjunction with a new address.(see table 5.) the reset command does not terminate the burst read operation. when it accesses the bank is programming or erasing, continuous burst read mode will output status da ta. and status data will be sustained until the system asserts ce high or reset low or avd low in conjunction with a new address. note that at least 10ns is needed to start next burst read op eration from terminating previous burst read operation in the case of asserting ce high. 8-,16-word linear burst read as well as the continuous linear burst mode, there are two(8 & 16 word) linear wrap, in which a fixed number of words are read from consecutive addresses. in these modes, the addresses for burst read are det ermined by the group within which the starting address falls. th e groups are sized according to the number of words read in a single burst sequence for a given mode.(see table. 7) as an example: in wrap mode case, if the starting address in the 8-word mode is 2h, the address range to be read would be 0-7h, and the wrap b urst sequence would be 2-3-4-5-6-7-0-1h. the burst sequence begins with the starting addres s written to the device, but wraps back to the first addres s in the selected group. in a similar manner, 16-word wrap mode begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. [table 7] burst address groups(wrap mode only) 8.4 output driver setting the device supports four kinds of output dr iver setting for matching the system chra cteristics. the users can tune the output d river impedance of the data and rdy outputs by address bits a20-a19. (see configuration regi ster table) the users can set the output driver strength indepe ndently for precise sys- tem characteristic matching. table 8 show s which output driver would be tuned and the strength according to a20-a19. upon power -up or reset, the reg- ister will revert to the default setting. burst mode group size group address ranges 8 word 8 words 0-7h, 8-fh, 10-17h, .... 16 word 16words 0-fh, 10-1fh, 20-2fh, .... - 13 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e 8.5 programmable wait state the programmable wait state feature indicates to the device the number of additional clock cycles that must elapse after avd is driven active for burst read mode. upon power up, the number of to tal initial access cycles defaults to eight. handshaking the handshaking feature allows the host syst em to simply monitor the rdy signal from the device to determine when the initial w ord of burst data is ready to be read. to set the number of initial cycle for optimal bur st mode, the host should use the programmable wait state configur ation.(see "set burst mode configuration register" for details.) the rising edge of rdy after oe goes low indicates the initial word of va lid burst data. using the autoselect command sequence the handshaking feature may be verified in the device. 8.6 set burst mode configuration register the device uses a configuration register to set the various burst parameters : the number of initial cycles for burst and burst read mode. the burst mode configuration register must be set before the device enters burst mode. the burst mode configuration register is loaded with a three- cycle command sequences. on the third cycle, the data should be c0 h, address bits a11-a0 should be 555h, and address bits a20-a12 set the code to be latched. the device will power up or after a hardware reset with th e default setting. [table 8] burst mode configuration register table note : initial wait state should be set according to it?s clock frequency. table 8 recommends the program wait state for each clock frequencies. not 100% tested 8.6.1 extended configuration register (option : k8a2615et(b)e only) the synchronous(burst) mode will start on the la st rising edge of the clk input while avd is held low after extended mode register setting to a12=1. [table 9] extended configuration register table 8.7 programmable wait state configuration this feature informs the device of the number of clock cycles that must elapse after avd is driven active before data will be available. this value is deter- mined by the input frequency of th e device. address bits a14-a12 determine the setting. (see burst mode configuration register table) the programmable wait state setting instructs the device to set a pa rticular number of clock cycles for the initial access in b urst mode. note that hardware reset will set the wait state to the default setting, that is 8 initial cycles. address bit function settings(binary) a20 output driver control 00 = driver multiplier : 1/3 01 = driver multiplier : 1/2 10 = driver multiplier : 1 (default) 11 = driver multiplier : 1.5 a19 a18 rdy active 1 = rdy active one clock cycle before data 0 = rdy active with data(default) a17 burst read mode 000 = continuous(default) 001 = 8-word linear with wrap 010 = 16-word linear with wrap 011 ~ 111 = reserve a16 a15 a14 programmable wait state 000 = data is valid on the 4th active clk edge after avd transition to vih (50/54mhz) 001 = data is valid on the 5th active clk edge after avd transition to vih (60/66/70mhz) 010 = data is valid on the 6th active clk edge after avd transition to vih (80/83mhz) 011 = data is valid on the 7th active clk edge after avd transition to vih (90/100mhz) 100 = data is valid on the 8th active clk edge after avd transition to vih (108mhz,default) 101 = reserve 110 = reserve 111 = reserve a13 a12 address bit function settings(binary) a12 read mode 0 = asynchronous read mode(default) 1 = synchronous burst read mode - 14 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e 8.8 burst read mode setting the device supports three different burst read modes : continuous linear mode, 8 and 16 word linear burst modes with wrap. 8.9 rdy configuration by default, the rdy pin will be high whenever there is valid data on the output. the device can be set so that rdy goes active one data cycle before active data. address bit a18 determine this setting. note that rdy always go high with valid data in case of word boundary cros sing. [table 10] burst address sequences 8.10 autoselect mode by writing the autoselect command sequences to the system, the device enters the autoselect mode. this mode can be read only by asynchronous read mode. the system can then read autoselect codes from the internal register(which is separate from the memory array). standard a synchronous read cycle timings apply in this mode. the device offers the autoselect mode to i dentify manufacturer and device type by reading a b inary code. in addition, this mode allows the host system to verify the block protec tion or unprotection. table 11 shows the address and data requiremen ts. the autoselect com- mand sequence may be written to an address within a bank that is in the read mode, erase-suspend-read mode or program-suspend-r ead mode. the autoselect command may not be written while t he device is actively programming or eras ing in the device. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that cont ains the address and the autoselect comman d. note that the block address is needed for the verification of block protection. the sy stem may read at any address within the same bank any number of times without initiat- ing another autoselect command sequence. and the burst read should be prohibited during autoselect mode. to terminate the autos elect operation, write reset command(f0h) into the command register. [table 11] autoselct mode description 8.11 standby mode when the ce and reset inputs are both held at v cc 0.2v or the system is not reading or writing, the device enters stand-by mode to minimize the power consumption. in this mode, the device outputs are placed in the high impedence state, independent of the oe input. when the device is in either of these standby modes, the device requires standard access time (tce ) for read access before it is ready to read data. if the de vice is deselected during erasure or programming, the dev ice draws active current until the operation is completed. i cc5 in the dc characteristics table represents the standby cur- rent specification. 8.12 automatic sleep mode the device features automatic sleep mode to minimize the device power consumption during both asynchronous and burst mode. when addresses remain stable for t aa +60ns, the device automatically enables this mode. the automatic sleep mode is independent of the ce , we , and oe control signals. in a sleep mode, output data is latched and always available to the system. when addresses are changed, the device provides new data without wait time. automatic sleep mode current is equal to standby mode current. 8.13 output disable mode when the oe input is at v ih , output from the device is disabled. t he outputs are placed in the high impedance state. start addr. burst address sequence continuous burst 8-word burst 16-word burst wrap 0 0-1-2-3-4-5-6... 0-1-2-3-4- 5-6-7 0-1-2-3-4-....-d-e-f 1 1-2-3-4-5-6-7... 1-2-3-4-5- 6-7-0 1-2-3-4-5-....-e-f-0 2 2-3-4-5-6-7-8... 2-3-4-5-6- 7-0-1 2-3-4-5-6-....-f-0-1 . . . . . . . . description address read data manufacturer id (da) + 00h ech device id (da) + 01h 2402h(top boot block), 2403h(bottom boot block) block protection/unprotection (ba) + 02h 01h (protected), 00h (unprotected) handshaking (da) + 03h 0h : handshaking, 1h : non-handshaking master locking bit indicator bit (ba) + 04h 01h(protected), 00h(unprotected) - 15 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e 8.14 block protection & unprotection to protect the block from accidental writ es, the block protection/unprotection command sequence is used. on power up, all block s in the device are pro- tected. to unprotect a block, the system must write the bloc k protection/unprotection command s equence. the first two cycles ar e written: addresses are don?t care and data is 60h. using the third cycle, the block addr ess (abp) and command (60h) is written, while specifying with addresses a6, a1 and a0 whether that block should be protected (a6 = v il, a1 = v ih , a0 = v il ) or unprotected (a6 = v ih, a1 = v ih , a0 = v il ). after the third cycle, the system can continue to protect or unprotect additi onal cycles, or exit the sequence by writing f0h (reset command). the device offers three types of data protection at the block level: ? the block protection/unprotection comma nd sequence disables or re- enables both program and erase operations in any block. ? when wp is at v il , the two outermost blocks are protected. ? when v pp is at v il , all blocks are protected. note that user never float the v pp and wp , that is, vpp is always connected with v ih , v il or v id and wp is v ih or v il . 8.15 hardware reset the device features a hardware method of resetting the device by the reset input. when the reset pin is held low(v il ) for at least a period of trp, the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for the dur ation of the reset pulse. the device also resets the internal state machine to asynch ronous read mode. to ensure data integrity, the interrupted operatio n should be reinitiated once the device is ready to accept another comma nd sequence. as previously noted, when reset is held at v ss 0.2v, the device enters standby mode. the reset pin may be tied to the system reset pin. if a system reset occu rs during the internal program or erase routine, the device wil l be auto- matically reset to the asynchronous read mode; this will enable the systems microprocessor to read the boot-up firmware from th e flash memory. if reset is asserted during a program or erase opera tion, the device requires a time of tready (during internal routines) before the de vice is ready to read data again. if reset is asserted when a program or erase operati on is not executing, the reset operation is completed within a time of tready (not during internal routines). trh is needed to read data after reset returns to v ih . refer to the ac characteristics tables for reset parameters and to figure 11 for the timing diagram. 8.16 software reset the reset command provides that the bank is reseted to read mode, erase-suspend-read mode or program-suspend-read mode. the add resses are in don?t care state. the reset command may be written between the se quence cycles in an erase command sequence before erasing begi ns, or in a pro- gram command sequence before programming begins . if the device begins erasure or progra mming, the reset command is ignored unti l the operation is completed. if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command re turns that bank to the erase-suspend-read mode. the reset command is valid between the s equence cycles in an autoselect command sequence. in an autose lect mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase suspend mode , writing the reset command returns that bank to the erase-suspend-read mode. also, if a bank entered the autoselect mode while in the program susp end mode, writing the reset command returns that bank to the program-suspend-read mode. if dq5 goes high during a program or an erase operation, writing the reset command returns the banks to the read mode. (or erase-suspend-read mode if the bank was in erase suspend) 8.17 program the k8a2815e can be programmed in units of a word. programming is wr iting 0's into the memory array by executing the internal p rogram routine. in order to perform the internal program routine, a four-cycle command sequence is necessary. the first two cycles are unlock cycl es. the third cycle is assigned for the program setup command. in the last cycle, the address of the memory location and the data to be programmed at that location are writ- ten. the device automatically generates adequate program pulses and veri fies the programmed cell margin by the internal program routine. during the execution of the routine, the system is not required to provi de further controls or timings. during the internal program routin e, commands written to the device will be ignored. note that a hardware reset during a program operation wi ll cause data corruption at the corresponding location. - 16 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e 8.18 accelerated program operation the device provides single word accelerat ed program operations through the vpp input. using this mode, faster manufacturing thr oughput at the factory is possible. when v id is asserted on the vpp input, the device automatically enters the unlock bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for program operations. by removing v id returns the device to normal opera- tion mode. note that read while accelerated programm and program suspend mode are not guaranteed single word accelerated program operation the system would use two-cycle program s equence (one-cycle (xxx - a0h) is for single word program command, and next one-cycle ( pa - pd) is for program address and data ). quadruple word accelerated program operation as well as single word accelerated program, the system would us e five-cycle program sequence (one-cycle (xxx - a5h) is for qua druple word program command, and four cycles are for program address and data). ? only four words programming is possible ? each program address must have the same a22~a2 address ? the device automatically generates adequate program pulses and ignores other command after program command ? program/erase cycling must be limited below 100cycles for optimum performance. ? read while write mode is not guaranteed requirements : ambient temperature : t a =30 c 10 c 8.19 unlock bypass the k8a2815e provides the unlock bypass m ode to save its operation time. this mode is possible for program, block erase and chi p erase operation. there are two methods to enter the unlock bypass mode. the mode is invoked by the unlock bypass command sequence or the asserti on of v id on v pp pin. unlike the standard program/erase command sequence that contai ns four/six bus cycles, the unlock bypass program/erase comm and sequence needs only two bus cycles. the unlock bypass mode is engaged by issuing the unlock bypa ss command sequence which is comprised o f three bus cycles. writing first two unlock cycles is followed by a third cycle containing the unl ock bypass command (20h). once the devi ce is in the unlock bypass mode, the unlock bypass program/erase command sequence is necessa ry. the unlock bypass program command sequence is comprised of only two bus cycles; writing the unlock bypass program command (a0h) is followed by the program address and data. this command sequence is t he only valid one for programming the device in the unlock bypass mode. also, t he unlock bypass erase command s equence is comprised of two bus cy cles; writing the unlock bypass block erase command(80h-30h) or writing the unlock bypass chip erase co mmand(80h-10h). this command sequences are the only valid ones for erasing the device in the unlock bypass mode. the unlock bypass rese t command sequence is the only valid command sequence to exit the unlock bypass mode. the unlock bypass reset command sequence cons ists of two bus cycles. the fi rst cycle must contain the d ata (90h). the sec- ond cycle contains only the data (00h). then, the device returns to the read mode. to enter the unlock bypass mode in hardware level, the v id also can be used. by assertion v id on the v pp pin, the device enters the unlock bypass mode. also, the all blocks are temporarily unprotected when the device using the v id for unlock bypass mode. to exit the unlock bypass mode, just remove the asserted v id from the v pp pin.(note that user never float the v pp , that is, vpp is always connected with v ih , v il or v id . ) . 8.20 chip erase to erase a chip is to write 1 s into the entire memory array by executing the internal erase routine. the chip erase requires six bus cycles to write the command sequence. the erase set-up command is wr itten after first two "unlock" cycles. t hen, there are two more write cycles pr ior to writing the chip erase command. the internal erase routine automatically pre-progr ams and verifies the entire memory for an all zero data patter n prior to erasing. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when dq7 is "1". after that the device returns to the read mode. 8.21 block erase to erase a block is to write 1 s into the desired memory block by executing the internal eras e routine. the block erase requi res six bus cycles to write the command sequence shown in table 6. after the first two "unlock" cycles, the erase set up command (80h) is written at the third c ycle. then there are two more "unlock" cycles followed by the bl ock erase command. the internal erase routi ne automatically pre-programs and verifies th e entire memory prior to erasing it. multiple blocks can be eras ed sequentially by writing the sixth bus-cycle . upon completion of the last cycle for the block erase, additional block address and the block erase command (30h ) can be written to perform the multi-block erase. for the multi-block erase, onl y sixth cycle(block address and 30h) is needed.(similarly, only sec ond cycle is needed in unlock by pass block erase.) an 50us (typical) "time windo w" is required between the block erase command writes. the block er ase command must be written within the 50us "time window", otherwise the block eras e command will be ignored. the 50us "time window" is reset when the falling edge of the we occurs within the 50us of "time wi ndow" to latch the block erase command. during the 50us of "time window", any command other than the block erase or the erase suspend co mmand written to the device wil l reset the device to read mode. after the 50us of "time window", the block erase command will initiate the internal erase routine to erase the selec ted blocks. any block erase address and command following the exceeded "time window" may or may not be accepted. no other commands will be recognized except the erase suspend command during block erase operation. the device provides accelerated erase operations through the vpp input. when v id is asserted on the vpp input, t he device automatically enters the unlock bypass mode, temporarily unprotec ts any protected blocks, and uses the higher voltage on the input to reduce the time r equired for erase. by removing v id returns the device to normal operation mode. - 17 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e 8.22 erase suspend / resume the erase suspend command interrupts the block erase to read or pr ogram data in a block that is not being erased. also, it is p ossible to protect or unprotect of the block that is not being erased in erase suspend mode. the erase su spend command is only valid during the block erase operation including the time window of 50us. the erase suspend command is not valid while the chip erase or the internal program routine sequence is running. when the erase suspend command is written during a block erase oper ation, the device requires a maximum of 20us(recovery time) to suspend the erase operation. therefore system must wait for 20us(recovery ti me) to read the data from the bank which include the block bein g erased. otherwise, system can read the data immediately from a bank which don?t include the block being erased without recovery time(max. 20us) af ter erase suspend command. and, after the maximum 20us recovery time, the device is availble for programming data in a block that is not being er ased. but, when the erase suspend command is written during the bl ock erase time window (50us), the device immediately terminates the block erase t ime window and sus- pends the erase operation. the system may also write the autos elect command sequence when the device is in the erase suspend m ode. when the erase resume command is executed, the bloc k erase operation will resume. when the eras e suspend or erase resume command is exec uted, the addresses are in don't care state. in erase suspend followed by resume operation, min. 200ns is needed for checking the busy st atus. in the program suspend mode, protect/unprotect command is prohibited. while erase operation can be suspended and resumed multiple times, a minimum 30us is required from resume to the next suspend. 8.23 program suspend / resume the device provides the program suspend/resu me mode. this mode is used to enable data read by suspending the program operation. the device accepts a program suspend command in program mode(including progr am operations performed during erase suspend) but other comman ds are ignored. after input of the program suspend command, 10us is needed to enter the program suspend read mode. therefore system m ust wait for 10us(recovery time) to read the data from the bank which incl ude the block being programmed. othwewise, system can read the dat a immediately from a bank which don't include block being programm ed without recovery time(max. 10us) afte r program suspend command. like an erase s uspend mode, the device can be returned to program mode by using a program resume command. in program suspend followed by resume operation, min. 200ns is needed for checking the busy status. while program operation can be suspended and resumed multiple time s, a minimum 30us is required from resume to the next suspend . 8.24 read while write operation the device is capable of reading data from one bank while writi ng in the other banks. this is so called the read while write o peration. an erase opera- tion may also be suspended to read from or program to another lo cation within the same bank(except the block being erased). the read while write operation is prohibited during the chip erase operation. figure 17 shows how read and write cycles may be initiated for simulta neous operation with zero latency. refer to the dc characteristics tabl e for read-while-write current specifications. 8.25 otp block region the otp block feature provides a 256-word flash memory region that enables permanent part identification through an electronic serial number (esn). the otp block is customer lockable and shi pped with itself unlocked, allowing customer s to untilize the that block in any manne r they choose. the cus- tomer-lockable otp block has the protection verify bit (dq0) set to a "0" for unlocked state or a "1" for locked state. the system accesses the otp block through a command sequence (see "enter otp block / exit otp block command sequence" at table 6). after the system has written the "enter otp block" command sequence, it may read the otp block by using the address (7fff00h~7fffffh, in top boot device),(000000h~0000ffh, in bottom boot device)normally and may check the protection verify bit (dq0 ) by using the "autoselect block protection ver- ify" command sequence with otp block address. this mode of operati on continues until the system i ssues the "exit otp block" com mand suquence, a hardware reset or until power is removed from the device. on pow er-up, or following a hardware reset, the device reverts to sen ding commands to main blocks. note that the accelerated function and unlock by pass modes are not availabl e when the otp block is enabled. customer lockable in a customer lockable device, the otp block is one-time progr ammable and can be locked only once. note that the accelerated pr ogramming and unlock bypass functions are not availabl e when programming the otp block. locking operat ion to the otp block is started by writ ing the "enter otp block" command sequence, and then the "block protection" command s qeunce (table 6) with an otp block address. hardware reset te rminates lock- ing operation, and then makes exiting from otp block. the lo cking operation has to be above 100us. (after 3rd cycle of protecti on command invoked, at least 100us wait time is required.) "exit otp block" commnad sequence and hardware re set makes locking operation finished and t hen exiting from otp block after 30us. the otp block lock operation must be used with caution since, once locked, there is no procedure available for unlocking and no ne of the bits in the otp block space can be modified in any way. suspend and resume operation are not supported during otp protect, nor is otp protect supported during any suspend operations. 8.26 write pulse glitch protection noise pulses of less than 5ns (typical) on oe , ce, avd or we do not initiate a write cycle. - 18 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e 8.27 low vcc write inhibit to avoid initiation of a write cycle during vcc power-up and pow er-down, a write cycle is lo cked out for vcc less than v lko . if the vcc < v lko (lock-out voltage), the command register and all internal program/erase circ uits are disabled. under this condition the device will reset itself to the read mode.sub- sequent writes will be ignored until the vcc level is greater than v lko . it is the user?s responsibility to ensure that the control pins are logically correct to prevent unintentional writes when vcc is above v lko. 8.28 logical inhibit write cycles are inhibite d by holding any one of oe = v il , ce = v ih or we = v ih . to initiate a write cycle, ce and we must be a logical zero while oe is a logical one. 8.29 power-up protection to avoid initiation of a write cycle during v cc power-up, reset low must be asserted during power-up. after reset goes high. the device is reset to the read mode. 8.30 flash memory status flags the k8a2815e has means to indicate its status of operation in t he bank where a program or erase operation is in processes. addr ess must include bank address being executed internal routine operation. the status is indicated by raising the dev ice status flag via corresponding dq pins. this status read is supported in burst mode and asynchronous mode. the status data can be read during burst read mode by using avd signal with a bank address. that means status read is supported in synchr onous mode. if status read is performed, the data provided in the burst read is identic al to the data in the initial access. to initiate the synchronous read again, a new address and avd pulse is needed after the host has completed status reads or the device has completed the program or erase operation. the corr esponding dq pins are dq7, dq6, dq5, dq3 and dq2. [table 12] hardware sequence flags note : 1) dq2 will toggle when the device performs successive read operations from the erase/program suspended block. 2) if dq5 is high (exceeded timing limits), successive reads from a problem block will cause dq2 to toggle. dq7 : data polling when an attempt to read the device is made while executing the inter nal program, the complement of the data is written to dq7 a s an indication of the routine in progress. when the routine is completed an attempt to access to the device will produce the true data written to dq7 . when a user attempts to read the block being erased or bank contains the block, dq7 wi ll be low. if the device is placed in the erase/program suspen d mode, the status can be detected via the dq7 pin. if the system tries to read an addres s which belongs to a block that is being erase suspended, dq7 wi ll be high. and, if the sys- tem tries to read an address which belongs to a block that is being program suspended, the output will be the true data of dq7 itself. if a non-erase-sus- pended or non-program-suspended block address is read, the device wi ll produce the true data to dq7. if an attempt is made to p rogram a protected block, dq7 outputs complements the data for approximately 1 s and the device then returns to the read mode without changing data in the block. if an attempt is made to erase a protected block, dq7 outputs comple ment data in approximately 100us and the device then returns to t he read mode without erasing the data in the block. status dq7 dq6 dq5 dq3 dq2 in progress programming dq7 toggle 0 0 1 block erase or chip erase 0 toggle 0 1 toggle erase suspend read erase suspended block 1100 toggle 1) erase suspend read non-erase sus- pended block data data data data data erase suspend program non-erase sus- pended block dq7 toggle 0 0 1 program suspend read program suspended block dq7100 toggle 1) program suspend read non- program suspended block data data data data data exceeded time limits programming dq7 toggle 1 0 no toggle block erase or chip erase 0 toggle 1 1 note 2 erase suspend program dq7 toggle 1 0 no toggle - 19 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e dq6 : toggle bit toggle bit is another option to detect whether an internal routine is in progress or co mpleted. once the device is at a busy st ate, dq6 will toggle. toggling dq6 will stop after the device completes it s internal routine. if the device is in the erase/program suspend mode, an attempt t o read an address that belongs to a block that is being erased or programmed will produce a high output of dq6. if an address belongs to a block that is not being erased or pro- grammed, toggling is halted and valid data is produced at dq6. if an attempt is made to program a protected block, dq6 toggles for approximately 1us and the device then returns to the read mode without changing the data in the block. if an attempt is made to erase a protected block, dq6 toggles for approximately 100 s and the device then returns to the read mode without erasing the data in the block. #oe or #ce should be toggled in each tog gle bit status read. dq5 : exceed timing limits if the internal program/erase routine extends beyond the timi ng limits, dq5 will go high, indi cating program/erase failure. dq3 : block erase timer the status of the multi-block erase operation can be detected via the dq3 pin. dq3 will go high if 50 s of the block erase time window expires. in this case, the internal erase routine will initiate the erase operat ion.therefore, the device will not accept further write commands until the erase operation is completed. dq3 is low if the block erase time window is not expired. within the block erase time window , an additional block er ase command (30h) can be accepted. to confirm that the block eras e command has been accepted, the software ma y check the status of dq3 following each block erase com- mand. dq2 : toggle bit 2 the device generates a toggling pulse in dq 2 only if an internal erase routine or an erase/program suspend is in progress. when the device executes the internal erase routine, dq2 toggles if the bank including an erasing block is read. although the internal erase routine is in the exceeded time lim- its, dq2 toggles if an erasing block in the exceeded time limits is read. when the device is in the erase/program suspend mode, dq2 toggles only if an address in the erasing or programming block is read. if a non-er asing or non-programmed block addr ess is read during the erase/ program suspend mode, then dq2 will produce valid data. dq2 will go high if the user tries to program a non-erase suspend block while the devic e is in the erase suspend mode. #oe or #ce should be toggled in each toggle bit status read. rdy: ready normally the rdy signal is used to indicate if new burst data is available at the rising edge of the clock cycle or not. if rdy is low state, data is not valid at expected time, and if high state, data is valid. note that, if ce is low and oe is high, the rdy is high state. figure 1: data polling algorithms figure 2: toggle bit algorithms start dq7 = data ? no dq5 = 1 ? fail pass yes dq7 = data ? no no yes read(dq0~dq7) valid address read(dq0~dq7) valid address yes start dq6 = toggle ? no dq5 = 1 ? fail pass no dq6 = toggle ? yes yes no read twice(dq0~dq7) valid address read(dq0~dq7) valid address yes read(dq0~dq7) valid address - 20 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e 9.0 common flash memory interface common flash memory interface is contrived to increase the compatibility of host system software. it provides the specific info rmation of the device, such as memory size and electrical f eatures. once this information has been obtained, the system software will know which command se ts to use to enable flash writes, block erases, and control the flash component. when the system writes the cfi command(98h) to address 55h , the de vice enters the cfi mode. and then if the system writes the address shown in table 13, the system can read the cfi data. query data are always presented on the lowest-order data outputs(dq0-7) only. in w ord(x16) mode, the upper data outputs(dq8-15) is 00h. to terminate this operation, the system must write the reset command. [table 13] common flash memory interface code description addresses (word mode) data query unique ascii string "qry" 10h 11h 12h 0051h 0052h 0059h primary oem command set 13h 14h 0002h 0000h address for primary extended table 15h 16h 0040h 0000h alternate oem command set (00h = none exists) 17h 18h 0000h 0000h address for alternate oem extended table (00h = none exists) 19h 1ah 0000h 0000h vcc min. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1bh 0017h vcc max. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1ch 0019h vpp(acceleration program) supply minimum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 1dh 0085h vpp(acceleration program) supply maximum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 1eh 0095h typical timeout per single word write 2 n us 1fh 0004h typical timeout for min. size buffer write 2 n us(00h = not supported) 20h 0000h typical timeout per i ndividual block erase 2 n ms 21h 000ah typical timeout for full chip erase 2 n ms(00h = not supported) 22h 0012h max. timeout for word write 2 n times typical 23h 0005h max. timeout for buffer write 2 n times typical 24h 0000h max. timeout per individual block erase 2 n times typical 25h 0004h max. timeout for full chip erase 2 n times typical(00h = not supported) 26h 0000h device size = 2 n byte 27h 0018h flash device interface description 28h 29h 0000h 0000h max. number of byte in multi-byte write = 2 n 2ah 2bh 0000h 0000h number of erase block regions within device 2ch 0002h - 21 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e description addresses (word mode) data erase block region 1 information bits 0~15: y+1=block number bits 16~31: block size= z x 256bytes 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 2 information 31h 32h 33h 34h 00feh 0000h 0000h 0001h erase block region 3 information 35h 36h 37h 38h 0000h 0000h 0000h 0000h erase block region 4 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h query-unique ascii string "pri" 40h 41h 42h 0050h 0052h 0049h major version number, ascii 43h 0032h minor version number, ascii 44h 0033h address sensitive unlock(bits 1-0) 0 = required, 1= not required silcon revision number(bits 7-2) 45h 0000h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 46h 0002h block protect 00 = not supported, 01 = supported 47h 0001h block temporary unprotect 00 = not supported, 01 = supported 48h 0000h block protect/unprotect scheme 00 = not supported, 01 = supported 49h 0001h simultaneous operation 00 = not supported, 01 = supported 4ah 0001h burst mode type 00 = not supported, 01 = supported 4bh 0001h page mode type 00 = not supported, 01 = 4 word page 02 = 8 word page 4ch 0002h top/bottom boot block flag 02h = bottom boot device, 03h = top boot device 4dh 0003h max. operating clock frequency (mhz ) 4eh 006ch rww(read while write) functionality restrict ion (00h = non exists , 01h = exists) 4fh 0000h handshaking 00 = not supported at both mode, 01 = supported at sync. mode 10 = supported at async. mode, 11 = supported at both mode 50h 0001h - 22 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e 10.0 absolute maximum ratings note : 1) minimum dc voltage is -0.5v on input/ output pins. during transitions, this level may fall to -1.5v for periods <20ns. maximum dc voltage is vcc+0.6v on input / output pins whic h, during transitions, may overshoot to vcc+1.5v for periods <20n s. 2) minimum dc input voltage is -0.5v on vpp . during transit ions, this level may fall to -1.5v for periods <20ns. maximum dc input voltage is +9.5v on vpp which, dur ing transitions, may overshoot to +11.0v for periods <20ns. 3) permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. ex posure to absolute maximum rating conditions for extended perio ds may affect reliability. 11.0 recommended operating conditions ( voltage reference to gnd ) 12.0 dc characteristics note : 1) maximum icc specifications are tested with vcc = vccmax. 2) icc active while internal erase or internal program is in progress. 3) device enters automatic sleep mode when addresses are stable for taa + 60ns. parameter symbol rating unit voltage on any pin relative to v ss vcc vcc -0.5 to +2.5 v v pp v in -0.5 to +9.5 all other pins -0.5 to +2.5 temperature under bias commercial t bias -10 to +125 c extended -25 to +125 storage temperature t stg -65 to +150 c short circuit output current i os 5ma operating temperature t a (commercial temp.) 0 to +70 c t a (extended temp.) -25 to + 85 c parameter symbol min typ. max unit supply voltage v cc 1.7 1.8 1.95 v supply voltage v ss 000v parameter symbol test conditions min typ max unit input leakage current i li v in =v ss to v cc , v cc =v cc max - 1.0 - + 1.0 a vpp leakage current i lip v cc =v cc max , v pp =v cc max - 1.0 - + 1.0 a v cc =v cc max , v pp =9.5v --35 a output leakage current i lo v out =v ss to v cc , v cc =v cc max, oe =v ih - 1.0 - + 1.0 a active burst read current i ccb1 ce =v il , oe =v ih (continuous burst, 66mhz) -2436ma active asynchronous read current i cc1 ce =v il , oe =v ih 10mhz - 27 40 ma active write current 2) i cc2 ce =v il , oe =v ih , we =v il , v pp =v ih -1530ma read while write current i cc3 ce =v il , oe =v ih -4070ma accelerated program current i cc4 ce =v il , oe =v ih , v pp =9.5v -1530ma standby current i cc5 ce = reset =v cc 0.2v -1550 a standby current during reset i cc6 reset = v ss 0.2v -1550 a automatic sleep mode 3) i cc7 ce =v ss 0.2v, other pins=v il or v ih v il = v ss 0.2v, v ih = v cc 0.2v -1550 a input low voltage v il -0.5 - 0.4 v input high voltage v ih v cc -0.4 - v cc +0.4 v output low voltage v ol i ol = 100 a , v cc =v cc min --0.1v output high voltage v oh i oh = -100 a , v cc =v cc min v cc -0.1 --v voltage for accelerated program v id 8.5 9.0 9.5 v low vcc lock-out voltage v lko --1.4v - 23 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e vcc power-up note : not 100% tested. switching waveforms figure 3: vcc power-up diagram parameter symbol all speed options unit min max vcc setup time t vcs 200 - s time between reset (high) and ce (low) t rh 200 - ns vcc/vccq reset ce t vcs t vccmin vih t rh - 24 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e 13.0 capacitance (ta = 25 c, vcc = 1.8v, f = 1.0mhz) note : capacitance is periodica lly sampled and not 100% tested. 14.0 ac test condition 15.0 ac characteristics 15.1 synchronous/burst read item symbol test condition min max unit input capacitance c in v in =0v -10pf output capacitance c out v out =0v -10pf control pin capacitance c in2 v in =0v -10pf parameter value input pulse levels 0v to v cc input rise and fall times 3ns(max)@66mhz, 2.5ns(max)@ 83mhz, 1.5ns(max)@108mhz input and output timing levels vcc/2 output load c l = 30pf address to address skew 3ns(max) parameter symbol 7b (54 mhz) 7c (66 mhz) 7d (83 mhz) 7e (108 mhz) unit min max min max min max min max initial access time t iaa -70-70-70-70ns burst access time valid clock to output delay t ba - 14.5 - 11 - 9 - 7 ns avd setup time to clk t avds 5-5-4-4-ns avd hold time from clk t avdh 2-2-2-2-ns address setup time to clk t acs 5-4-4-3.5-ns address hold time from clk t ach 7-6-5-2-ns data hold time from next clock cycle t bdh 4-3-3-2-ns output enable to data t oe -20-20-20-20ns output enable to rdy valid t oer - 14.5 - 11 - 9 - 7 ns ce disable to high z t cez - 15 - 15 - 11 - 8.5 ns oe disable to high z t oez -9-9-9-9ns ce setup time to clk t ces 6 - 6 - 4.5 - 4.5 - ns ce enable to rdy active t rdy -7-7-7-7ns clk to rdy setup time t rdya - 14.5 - 11 - 9 - 7 ns rdy setup time to clk t rdys 4-3-3-2-ns clk period t clk 18.5 - 15.1 - 12.05 - 9.26 - ns clk high or low time t clkh/l 0.4x t clk 0.6x t clk 0.4x t clk 0.6x t clk 0.4x t clk 0.6x t clk 0.4x t clk 0.6x t clk ns clk fall or rise time t clkhcl - 3 - 3 - 2.5 - 1.5 ns 0v v cc v cc /2 v cc /2 input & output test point output load device under te s t * c l = 30pf including scope and jig capacitance input pulse and test point (including clk characterization) - 25 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e switching waveforms figure 4: continuous burst mode read (66mhz) note : 1) in order to avoid a bus conflict the oe si gnal is enabled on the next rising edge after avd is going high. figure 5: continuous burst mode read (108 mhz) note : 1) in order to avoid a bus conflict the oe signal is enabled on the next rising edge after avd is going high. t ces t avds t avdh t acs t ach t iaa t ba t bdh t cez t oez hi-z hi-z hi-z da da+1 da+2 da+n aa da+3 t rdys 15.2ns typ(66mhz). da+4 da+5 da+6 5 cycles for initial access shown. cr setting : a14=0, a13=0, a12=1 ce clk avd oe dq0: dq15 rdy a0-a22 1 2 3 5 t rdya t oer t rdy t avds 4 t ces t avds t avdh t acs t ach t iaa t ba t bdh t cez t oez hi-z hi-z hi-z da da+1 da+2 da+n aa da+3 t rdys 9.25ns typ(108mhz). da+4 da+5 da+6 8 cycles for initial access shown. cr setting : a14=1, a13=0, a12=0 ce clk avd oe dq0: dq15 rdy a0-a22 1 2 3 4 6 7 8 t rdya t oer t rdy t avds - 26 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e switching waveforms figure 6: 8 word linear burst mode with wrap around (108mhz) t ces t avds t avdh t acs t ach t iaa t ba t bdh hi-z aa t rdys 9.25ns typ(108mhz). ce clk avd oe dq0: dq15 rdy a0-a22 8 cycles for initial access shown. cr setting : a14=1, a13=0, a12=0 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 t rdya 1 2 3 4 6 7 5 8 t oer t rdy t avds figure 7: 8 word linear burst with rdy set one cycle before data (wrap around mode, cr setting : a18=1) t ces t avds t avdh t acs t ach t iaa t ba t bdh hi-z aa t rdys 9.25ns typ(108mhz). ce clk avd oe dq0: dq15 rdy a0-a22 8 cycles for initial access shown. cr setting : a14=1, a13=0, a12=0 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 | | | | | | | | | 1 2 3 4 6 7 8 t rdya t oer t rdy t avds - 27 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e switching waveforms figure 8: 16 word linear burst mode with wrap around (108mhz) 15.2 asynchronous read note : not 100% tested. parameter symbol all speed option unit min max access time from ce low t ce -70ns asynchronous access time t aa -70ns page address access time t pa -20ns output hold time from address, ce or oe t oh 3-ns avd low setup time to ce enable t avdcs 0-ns avd low hold time from ce disable t avdch 0-ns output enable to output valid t oe -20ns output enable hold time read t oeh 0-ns toggle and data polling 10 - ns output disable to high z(note) t oez -9ns t ces t avds t avdh t acs t ach t iaa t ba t bdh t cez t oez hi-z hi-z hi-z aa t rdys 9.25ns typ(108mhz). ce clk avd oe dq0: dq15 rdy a0-a22 8 cycles for initial access shown. cr setting : a14=1, a13=0, a12=0 d7 d6 d8 d9 d10 d15 d0 1 2 3 4 6 7 8 5 t rdya t oer t rdy t avds - 28 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e switching waveforms asynchronous mode read figure 9: asynchronous mode read note : 1) va=valid read address, rd=read data. asynchronous mode may not support read following four sequential invalid read condition within 200ns. 2) clk "high" should be prohibited in as ynchronous read mode start (from ce low). switching waveforms page read operations figure 10: asynchronous page mode read note : clk "high" should be prohibited in asynchronous read mode start (from ce low). t oe va valid rd t ce t oeh t oez ce oe we dq0-dq15 a0-a22 t aa clk v il avd t avdcs t avdch t oe va t ce t oeh t oez ce oe we dq0-dq15 a3-a22 t aa clk v il avd t avdcs t avdch a0-a2 aa ab ac da db dh ah t pa t oh - 29 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e ac characteristics 15.3 hardware reset( reset ) note: not 100% tested. switching waveforms reset timings not during internal routines reset timings during internal routines figure 11: reset timings parameter symbol all speed options unit min max reset pin low(during internal routines) to read mode* t ready -20 s reset pin low(not during internal routines) to read mode (note) t ready - 500 ns reset pulse width* t rp 200 - ns reset high time before read (note) t rh 200 - ns t rh ce , oe reset t rp t ready t ready ce , oe reset t rp - 30 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e ac characteristics 15.4 erase/program operation note : 1) not 100% tested. 2) in write timing, addresses are latched on the falling edge of we . 3) include the preprogramming time. 16.0 flash erase/program performance note : 1) 25 c, vcc = 1.8v, 100,000 cycles, typical pattern. 2) system-level overhead is defined as the time required to execute the two or four bus cycle command necessary to program each word. in the preprogramming step of the internal erase routine, all words are programmed to 00h before erasure. 3) 100k program/erase cycle in all bank parameter symbol all speed option unit min typ max we cycle time 1) t wc 60 - - ns address setup time 2) t as 0--ns address hold time 2) t ah 30 - - ns data setup time t ds 30 - - ns data hold time t dh 0--ns read recovery time before write t ghwl 0--ns ce setup time t cs 0--ns ce hold time t ch 0--ns we pulse width t wp 30 - - ns we pulse width high t wph 30 - - ns latency between read and write operations t sr/w 0--ns word programming operation t pgm -11.5- s accelerated single word programming operation t accpgm -6.5- s accelerated quad word programming operation t accpgm_quad -6.5- s block erase operation 3) t bers -0.7-sec vpp rise and fall time t vpp 500 - - ns vpp setup time (during accelerated programming) t vps 1-- s parameter limits unit comments min. typ. max. block erase time 32 kword - 0.7 14 sec includes 00h programming prior to erasure 4 kword - 0.2 4 chip erase time - 180 - word programming time - 11.5 210 s excludes system level overhead accelerated sinlge programming time (@word) - 6.5 120 accelerated quad programming time (@word) 1.6 30 s chip programming time - 97 - sec accelerated single word chip programming time - 55 - accelerated quad word chip programming time - 13.5 - sec erase/program endurance 3) 100,000 - - cycles minimum 100,000 cycles guaran- teed in all bank - 31 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e switching waveforms program operations note : 1) pa = program address, pd = program data, va = valid address for reading status bits. 2) ?in progress? and ?complete? refer to status of program operation. 3) a16?a22 are don?t care during command sequence unlock cycles. 4) status reads in this figure is asynchronous read , but status read in synchr onous mode is also supported. 5) to check program status - address should be toggled (1st va to 2nd va) or #ce shoul d be toggled between 1st and 2nd va (if 2nd va is not changed). figure 12: program operation timing program command sequence (last two cycles) a0:a22 we ce clk t ah t ds t dh t ch t wp t cs t wph t wc t pgm pa 1st va 2nd va in progress complete pd a0h 555h dq0-dq15 oe v cc read status data (note 5) v il t as - 32 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e switching waveforms erase operation note : 1) ba is the block address for block erase. 2) address bits a16?a22 are don?t cares during unlock cycles in the command sequence. 3) status reads in this figure is asynchronous read , but status read in synchr onous mode is also supported. 4) avd setup/hold time to ce enable are same to asynchronous mode read 5) to check erase status - address should be toggled (1st va to 2nd va) or #ce shoul d be toggled between 1st and 2nd va (if 2nd va is not changed). figure 13: chlp/block erase operations erase command sequence (last two cycles) a0:a22 we ce t ds t dh t ch t bers ba 1st va 2nd va in progress complete 30h 55h 2aah dq0-dq15 oe v cc read status data (note 5) 555h for chip erase 10h for chip erase t wp t cs t wph t wc clk v il t ah t as - 33 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e switching waveforms unlock bypass program operations(accelerated program) unlock bypass block erase operations note : 1) vpp can be left high for subsequent programming pulses. 2) use setup and hold times from conventional program operations. 3) unlock bypass program/erase commands can be used when the vid is applied to vpp. 4) avd setup/hold time to ce enable are same to asynchronous mode read figure 14: unlock bypass operation timings ce oe a0:a22 v pp we dq0-dq15 1us t vps v il or v ih v id t vpp pa don?t care a0h pd don?t care don?t care ce oe a0:a22 v pp we dq0-dq15 1us t vps v il or v ih v id t vpp ba don?t care 80h 30h don?t care 555h for chip erase 10h for chip erase don?t care - 34 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e switching waveforms data polling operations note : 1) va = valid address. when the internal routine operation is complete, and data polling will output true data. figure 15: data polling timings (during internal routine) toggle bit operations note : 1) va = valid address. when the internal routine operation is complete, the toggle bits will stop toggling. figure 16: toggle bit timings(during internal routine) t ces t avds t avdh t acs t ach t iaa hi-z ce clk avd oe dq0-dq15 rdy va a0-a22 t rdys status data va status data t ces t avds t avdh t acs t ach t iaa hi-z ce clk avd oe dq0-dq15 rdy va a0-a22 t rdys status data va status data - 35 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e switching waveforms read while write operations figure 17: read while write operation note : 1) breakpoints in waveforms indicate that system may alternatel y read array data from the ?non-busy bank? and checking the stat us of the program or erase operation in the ?busy? bank. t wc ce oe we dq0-dq15 a0-a22 pd/30h 555h aah pa/ba ra ra rd rd last cycle in program or block erase command sequence read status in same bank and/or array data from other bank t rc t rc t wc t oe t oeh t wph t wp t aa t oeh t ds t dh t sr/w t ghwl command sequences program or erase begin another - 36 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e 17.0 crossing of first word boundary in burst read mode the additional clock insertion for word boundary is needed only at the fi rst crossing of word boundary. this means that no addi tional clock cycle is needed from 2nd word boundary crossing to the end of continuous burst read. also, the number of additional clock cycle for the first w ord boundary can varies from zero to seven cycles, and the ex act number of additional clock cycle depends on the starting address of burst read. the rule to determine the additional clock cyc le is as follows. all addresses can be divided into 8 groups. the applied rule is "the residue obtained when the address is divided by 8" or "three l sb bits of address". using this rule, all address can be divided by 8 different groups as shown in below table. for simplicity of terminology, "8n" stands for the address of which the residue is "0"(or the three lsb bits are "000") and "8n+1" for the address of which the residue is "1"(or the three lsb bits are "001"), etc. the additional clock cycles for first word boundary crossing are zero, one, two ... or seven when the burst read start from "8n " address, "8n+1" address, "8n+2" address .... or "8n+7" address respectively. starting address vs. additional clock cycles for first word boundary case 1 : start from "8n" address group note : 1) address boundary occurs every 16 words beginning at address 00000fh , 00001fh , 00002fh , etc. 2) address 000000h is also a boundary crossing. 3) no additional clock cycles are needed except for 1st boundary crossing. figure 18: crossing of first word boundary in burst read mode. srarting address group for burst read the residue of (address/8) lsb bits of address additional clock cycles for first word boundary a14~a12 "000" valid data : 4th a14~a12 "001" valid data : 5th a14~a12 "010" valid a14~a12 "011" valid a14~a12 "100" valid 8n 0 000 0 cycle 0 cycle 0 cycle 0 cycle 0 cycle 8n+1 1 001 0 cycle 0 cycle 0 cycle 0 cycle 1 cycle 8n+2 2 010 0 cycle 0 cycle 0 cycle 1 cycle 2 cycle 8n+3 3 011 0 cycle 0 cycle 1 cycle 2 cycle 3 cycle 8n+4 4 100 0 cycle 1 cycle 2 cycle 3 cycle 4 cycle 8n+5 5 101 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 8n+6 6 110 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 8n+7 7 111 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8th rising edge clk (108mhz) cr setting : a14=1, a13=0, a12=0 ce oe rdy clk data bus avd t cez t oez t oer 38 39 40 41 42 43 no additional cycle for first word boundary 3a 3e 3f a0-a22 39 40 41 42 3f 38 3d 3e - 37 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e case2 : start from "8n+1" address group case 3 : start from "8n+2" address group note : 1) address boundary occurs every 16 words beginning at address 00000fh , 00001fh , 00002fh , etc. 2) address 000000h is also a boundary crossing. 3) no additional clock cycles are needed except for 1st boundary crossing. figure 19: crossing of first word boundary in burst read mode. ce oe rdy clk avd t cez t oez t oer 39 3a 41 42 43 44 additional 1 cycle for first word boundary 3b 40 8th rising edge clk (108mhz) cr setting : a14=1, a13=0, a12=0 data bus a0-a22 3a 41 42 43 39 3f 40 ce oe rdy clk avd t cez t oez t oer 3a 3b 41 42 43 additional 2 cycle for first word boundary 3c 8th rising edge clk (108mhz) cr setting : a14=1, a13=0, a12=0 data bus a0-a22 40 41 42 3a 3b 3f 40 - 38 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e case4 : start from "8n+7" address group note : 1) address boundary occurs every 16 words beginning at address 00000fh , 00001fh , 00002fh , etc. 2) address 000000h is also a boundary crossing. 3) no additional clock cycles are needed except for 1st boundary crossing. figure 20: crossing of first word boundary in burst read mode. ce oe rdy clk avd t oer 3f 40 41 additional 7 cycle for first word boundary 8th rising edge clk (108mhz) cr setting : a14=1, a13=0, a12=0 data bus a0-a22 40 41 3f - 39 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e [table 14] top boot block address table(K8A2815ETE) bank block block size (x16) address range bank 0 ba262 4 kwords 7ff000h-7fffffh ba261 4 kwords 7fe000h-7fefffh ba260 4 kwords 7fd000h-7fdfffh ba259 4 kwords 7fc000h-7fcfffh ba258 4 kwords 7fb000h-7fbfffh ba257 4 kwords 7fa000h-7fafffh ba256 4 kwords 7f9000h-7f9fffh ba255 4 kwords 7f8000h-7f8fffh ba254 32 kwords 7f0000h-7f7fffh ba253 32 kwords 7e8000h-7effffh ba252 32 kwords 7e0000h-7e7fffh ba251 32 kwords 7d8000h-7dffffh ba250 32 kwords 7d0000h-7d7fffh ba249 32 kwords 7c8000h-7cffffh ba248 32 kwords 7c0000h-7c7fffh ba247 32 kwords 7b8000h-7bffffh ba246 32 kwords 7b0000h-7b7fffh ba245 32 kwords 7a8000h-7affffh ba244 32 kwords 7a0000h-7a7fffh ba243 32 kwords 798000h-79ffffh ba242 32 kwords 790000h-797fffh ba241 32 kwords 788000h-78ffffh ba240 32 kwords 780000h-787fffh bank 1 ba239 32 kwords 778000h-77ffffh ba238 32 kwords 770000h-777fffh ba237 32 kwords 768000h-76ffffh ba236 32 kwords 760000h-767fffh ba235 32 kwords 758000h-75ffffh ba234 32 kwords 750000h-757fffh ba233 32 kwords 748000h-74ffffh ba232 32 kwords 740000h-747fffh ba231 32 kwords 738000h-73ffffh ba230 32 kwords 730000h-737fffh ba229 32 kwords 728000h-72ffffh ba228 32 kwords 720000h-727fffh ba227 32 kwords 718000h-71ffffh ba226 32 kwords 710000h-717fffh ba225 32 kwords 708000h-70ffffh ba224 32 kwords 700000h-707fffh bank 2 ba223 32 kwords 6f8000h-6fffffh ba222 32 kwords 6f0000h-6f7fffh ba221 32 kwords 6e8000h-6effffh ba220 32 kwords 6e0000h-6e7fffh ba219 32 kwords 6d8000h-6dffffh - 40 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e bank block block size (x16) address range bank 2 ba218 32 kwords 6d0000h-6d7fffh ba217 32 kwords 6c8000h-6cffffh ba216 32 kwords 6c0000h-6c7fffh ba215 32 kwords 6b8000h-6bffffh ba214 32 kwords 6b0000h-6b7fffh ba213 32 kwords 6a8000h-6affffh ba212 32 kwords 6a0000h-6a7fffh ba211 32 kwords 698000h-69ffffh ba210 32 kwords 690000h-697fffh ba209 32 kwords 688000h-68ffffh ba208 32 kwords 680000h-687fffh bank 3 ba207 32 kwords 678000h-67ffffh ba206 32 kwords 670000h-677fffh ba205 32 kwords 668000h-66ffffh ba204 32 kwords 660000h-667fffh ba203 32 kwords 658000h-65ffffh ba202 32 kwords 650000h-657fffh ba201 32 kwords 648000h-64ffffh ba200 32 kwords 640000h-647fffh ba199 32 kwords 638000h-63ffffh ba198 32 kwords 630000h-637fffh ba197 32 kwords 628000h-62ffffh ba196 32 kwords 620000h-627fffh ba195 32 kwords 618000h-61ffffh ba194 32 kwords 610000h-617fffh ba193 32 kwords 608000h-60ffffh ba192 32 kwords 600000h-607fffh bank 4 ba191 32 kwords 5f8000h-5fffffh ba190 32 kwords 5f0000h-5f7fffh ba189 32 kwords 5e8000h-5effffh ba188 32 kwords 5e0000h-5e7fffh ba187 32 kwords 5d8000h-5dffffh ba186 32 kwords 5d0000h-5d7fffh ba185 32 kwords 5c8000h-5cffffh ba184 32 kwords 5c0000h-5c7fffh ba183 32 kwords 5b8000h-5bffffh ba182 32 kwords 5b0000h-5b7fffh ba181 32 kwords 5a8000h-5affffh ba180 32 kwords 5a0000h-5a7fffh ba179 32 kwords 598000h-59ffffh ba178 32 kwords 590000h-597fffh ba177 32 kwords 588000h-58ffffh ba176 32 kwords 580000h-587fffh bank 5 ba175 32 kwords 578000h-57ffffh - 41 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e bank block block size (x16) address range bank 5 ba174 32 kwords 570000h-577fffh ba173 32 kwords 568000h-56ffffh ba172 32 kwords 560000h-567fffh ba171 32 kwords 558000h-55ffffh ba170 32 kwords 550000h-557fffh ba169 32 kwords 548000h-54ffffh ba168 32 kwords 540000h-547fffh ba167 32 kwords 538000h-53ffffh ba166 32 kwords 530000h-537fffh ba165 32 kwords 528000h-52ffffh ba164 32 kwords 520000h-527fffh ba163 32 kwords 518000h-51ffffh ba162 32 kwords 510000h-517fffh ba161 32 kwords 508000h-50ffffh ba160 32 kwords 500000h-507fffh bank 6 ba159 32 kwords 4f8000h-4fffffh ba158 32 kwords 4f0000h-4f7fffh ba157 32 kwords 4e8000h-4effffh ba156 32 kwords 4e0000h-4e7fffh ba155 32 kwords 4d8000h-4dffffh ba154 32 kwords 4d0000h-4d7fffh ba153 32 kwords 4c8000h-4cffffh ba152 32 kwords 4c0000h-4c7fffh ba151 32 kwords 4b8000h-4bffffh ba150 32 kwords 4b0000h-4b7fffh ba149 32 kwords 4a8000h-4affffh ba148 32 kwords 4a0000h-4a7fffh ba147 32 kwords 498000h-49ffffh ba146 32 kwords 490000h-497fffh ba145 32 kwords 488000h-48ffffh ba144 32 kwords 480000h-487fffh bank 7 ba143 32 kwords 478000h-47ffffh ba142 32 kwords 470000h-477fffh ba141 32 kwords 468000h-46ffffh ba140 32 kwords 460000h-467fffh ba139 32 kwords 458000h-45ffffh ba138 32 kwords 450000h-457fffh ba137 32 kwords 448000h-44ffffh ba136 32 kwords 440000h-447fffh ba135 32 kwords 438000h-43ffffh ba134 32 kwords 430000h-437fffh ba133 32 kwords 428000h-42ffffh ba132 32 kwords 420000h-427fffh ba131 32 kwords 418000h-41ffffh ba130 32 kwords 410000h-417fffh - 42 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e bank block block size (x16) address range bank 7 ba129 32 kwords 408000h-40ffffh ba128 32 kwords 400000h-407fffh bank 8 ba127 32 kwords 3f8000h-3fffffh ba126 32 kwords 3f0000h-3f7fffh ba125 32 kwords 3e8000h-3effffh ba124 32 kwords 3e0000h-3e7fffh ba123 32 kwords 3d8000h-3dffffh ba122 32 kwords 3d0000h-3d7fffh ba121 32 kwords 3c8000h-3cffffh ba120 32 kwords 3c0000h-3c7fffh ba119 32 kwords 3b8000h-3bffffh ba118 32 kwords 3b0000h-3b7fffh ba117 32 kwords 3a8000h-3affffh ba116 32 kwords 3a0000h-3a7fffh ba115 32 kwords 398000h-39ffffh ba114 32 kwords 390000h-397fffh ba113 32 kwords 388000h-38ffffh ba112 32 kwords 380000h-387fffh bank 9 ba111 32 kwords 378000h-37ffffh ba110 32 kwords 370000h-377fffh ba109 32 kwords 368000h-36ffffh ba108 32 kwords 360000h-367fffh ba107 32 kwords 358000h-35ffffh ba106 32 kwords 350000h-357fffh ba105 32 kwords 348000h-34ffffh ba104 32 kwords 340000h-347fffh ba103 32 kwords 338000h-33ffffh ba102 32 kwords 330000h-337fffh ba101 32 kwords 328000h-32ffffh ba100 32 kwords 320000h-327fffh ba99 32 kwords 318000h-31ffffh ba98 32 kwords 310000h-317fffh ba97 32 kwords 308000h-30ffffh ba96 32 kwords 300000h-307fffh bank 10 ba95 32 kwords 2f8000h-2fffffh ba94 32 kwords 2f0000h-2f7fffh ba93 32 kwords 2e8000h-2effffh ba92 32 kwords 2e0000h-2e7fffh ba91 32 kwords 2d8000h-2dffffh ba90 32 kwords 2d0000h-2d7fffh ba89 32 kwords 2c8000h-2cffffh ba88 32 kwords 2c0000h-2c7fffh ba87 32 kwords 2b8000h-2bffffh ba86 32 kwords 2b0000h-2b7fffh ba85 32 kwords 2a8000h-2affffh - 43 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e bank block block size (x16) address range bank 10 ba84 32 kwords 2a0000h-2a7fffh ba83 32 kwords 298000h-29ffffh ba82 32 kwords 290000h-297fffh ba81 32 kwords 288000h-28ffffh ba80 32 kwords 280000h-287fffh bank 11 ba79 32 kwords 278000h-27ffffh ba78 32 kwords 270000h-277fffh ba77 32 kwords 268000h-26ffffh ba76 32 kwords 260000h-267fffh ba75 32 kwords 258000h-25ffffh ba74 32 kwords 250000h-257fffh ba73 32 kwords 248000h-24ffffh ba72 32 kwords 240000h-247fffh ba71 32 kwords 238000h-23ffffh ba70 32 kwords 230000h-237fffh ba69 32 kwords 228000h-22ffffh ba68 32 kwords 220000h-227fffh ba67 32 kwords 218000h-21ffffh ba66 32 kwords 210000h-217fffh ba65 32 kwords 208000h-20ffffh ba64 32 kwords 200000h-207fffh bank 12 ba63 32 kwords 1f8000h-1fffffh ba62 32 kwords 1f0000h-1f7fffh ba61 32 kwords 1e8000h-1effffh ba60 32 kwords 1e0000h-1e7fffh ba59 32 kwords 1d8000h-1dffffh ba58 32 kwords 1d0000h-1d7fffh ba57 32 kwords 1c8000h-1cffffh ba56 32 kwords 1c0000h-1c7fffh ba55 32 kwords 1b8000h-1bffffh ba54 32 kwords 1b0000h-1b7fffh ba53 32 kwords 1a8000h-1affffh ba52 32 kwords 1a0000h-1a7fffh ba51 32 kwords 198000h-19ffffh ba50 32 kwords 190000h-197fffh ba49 32 kwords 188000h-18ffffh ba48 32 kwords 180000h-187fffh bank 13 ba47 32 kwords 178000h-17ffffh ba46 32 kwords 170000h-177fffh ba45 32 kwords 168000h-16ffffh ba44 32 kwords 160000h-167fffh ba43 32 kwords 158000h-15ffffh ba42 32 kwords 150000h-157fffh ba41 32 kwords 148000h-14ffffh ba40 32 kwords 140000h-147fffh - 44 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e [table 15] top boot block otp addresses table after entering otp block, any issued addresses should be in the range of otp block address bank block block size (x16) address range bank 13 ba39 32 kwords 138000h-13ffffh ba38 32 kwords 130000h-137fffh ba37 32 kwords 128000h-12ffffh ba36 32 kwords 120000h-127fffh ba35 32 kwords 118000h-11ffffh ba34 32 kwords 110000h-117fffh ba33 32 kwords 108000h-10ffffh ba32 32 kwords 100000h-107fffh bank 14 ba31 32 kwords 0f8000h-0fffffh ba30 32 kwords 0f0000h-0f7fffh ba29 32 kwords 0e8000h-0effffh ba28 32 kwords 0e0000h-0e7fffh ba27 32 kwords 0d8000h-0dffffh ba26 32 kwords 0d0000h-0d7fffh ba25 32 kwords 0c8000h-0cffffh ba24 32 kwords 0c0000h-0c7fffh ba23 32 kwords 0b8000h-0bffffh ba22 32 kwords 0b0000h-0b7fffh ba21 32 kwords 0a8000h-0affffh ba20 32 kwords 0a0000h-0a7fffh ba19 32 kwords 098000h-09ffffh ba18 32 kwords 090000h-097fffh ba17 32 kwords 088000h-08ffffh ba16 32 kwords 080000h-087fffh bank 15 ba15 32 kwords 078000h-07ffffh ba14 32 kwords 070000h-077fffh ba13 32 kwords 068000h-06ffffh ba12 32 kwords 060000h-067fffh ba11 32 kwords 058000h-05ffffh ba10 32 kwords 050000h-057fffh ba9 32 kwords 048000h-04ffffh ba8 32 kwords 040000h-047fffh ba7 32 kwords 038000h-03ffffh ba6 32 kwords 030000h-037fffh ba5 32 kwords 028000h-02ffffh ba4 32 kwords 020000h-027fffh ba3 32 kwords 018000h-01ffffh ba2 32 kwords 010000h-017fffh ba1 32 kwords 008000h-00ffffh ba0 32 kwords 000000h-007fffh otp block address a22 ~ a8 block size (x16) address range 7fffh 256words 7fff00h-7fffffh - 45 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e [table 16] bottom boot block address (k8a2815ebe) bank block block size (x16) address range bank 15 ba262 32 kwords 7f8000h-7fffffh ba261 32 kwords 7f0000h-7f7fffh ba260 32 kwords 7e8000h-7effffh ba259 32 kwords 7e0000h-7e7fffh ba258 32 kwords 7d8000h-7dffffh ba257 32 kwords 7d0000h-7d7fffh ba256 32 kwords 7c8000h-7cffffh ba255 32 kwords 7c0000h-7c7fffh ba254 32 kwords 7b8000h-7bffffh ba253 32 kwords 7b0000h-7b7fffh ba252 32 kwords 7a8000h-7affffh ba251 32 kwords 7a0000h-7a7fffh ba250 32 kwords 798000h-79ffffh ba249 32 kwords 790000h-797fffh ba248 32 kwords 788000h-78ffffh ba247 32 kwords 780000h-787fffh bank 14 ba246 32 kwords 778000h-77ffffh ba245 32 kwords 770000h-777fffh ba244 32 kwords 768000h-76ffffh ba243 32 kwords 760000h-767fffh ba242 32 kwords 758000h-75ffffh ba241 32 kwords 750000h-757fffh ba240 32 kwords 748000h-74ffffh ba239 32 kwords 740000h-747fffh ba238 32 kwords 738000h-73ffffh ba237 32 kwords 730000h-737fffh ba236 32 kwords 728000h-72ffffh ba235 32 kwords 720000h-727fffh ba234 32 kwords 718000h-71ffffh ba233 32 kwords 710000h-717fffh ba232 32 kwords 708000h-70ffffh ba231 32 kwords 700000h-707fffh bank 13 ba230 32 kwords 6f8000h-6fffffh ba229 32 kwords 6f0000h-6f7fffh ba228 32 kwords 6e8000h-6effffh ba227 32 kwords 6e0000h-6e7fffh ba226 32 kwords 6d8000h-6dffffh - 46 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e bank block block size (x16) address range bank 13 ba225 32 kwords 6d0000h-6d7fffh ba224 32 kwords 6c8000h-6cffffh ba223 32 kwords 6c0000h-6c7fffh ba222 32 kwords 6b8000h-6bffffh ba221 32 kwords 6b0000h-6b7fffh ba220 32 kwords 6a8000h-6affffh ba219 32 kwords 6a0000h-6a7fffh ba218 32 kwords 698000h-69ffffh ba217 32 kwords 690000h-697fffh ba216 32 kwords 688000h-68ffffh ba215 32 kwords 680000h-687fffh bank 12 ba214 32 kwords 678000h-67ffffh ba213 32 kwords 670000h-677fffh ba212 32 kwords 668000h-66ffffh ba211 32 kwords 660000h-667fffh ba210 32 kwords 658000h-65ffffh ba209 32 kwords 650000h-657fffh ba208 32 kwords 648000h-64ffffh ba207 32 kwords 640000h-647fffh ba206 32 kwords 638000h-63ffffh ba205 32 kwords 630000h-637fffh ba204 32 kwords 628000h-62ffffh ba203 32 kwords 620000h-627fffh ba202 32 kwords 618000h-61ffffh ba201 32 kwords 610000h-617fffh ba200 32 kwords 608000h-60ffffh ba199 32 kwords 600000h-607fffh bank 11 ba198 32 kwords 5f8000h-5fffffh ba197 32 kwords 5f0000h-5f7fffh ba196 32 kwords 5e8000h-5effffh ba195 32 kwords 5e0000h-5e7fffh ba194 32 kwords 5d8000h-5dffffh ba193 32 kwords 5d0000h-5d7fffh ba192 32 kwords 5c8000h-5cffffh ba191 32 kwords 5c0000h-5c7fffh ba190 32 kwords 5b8000h-5bffffh ba189 32 kwords 5b0000h-5b7fffh ba188 32 kwords 5a8000h-5affffh ba187 32 kwords 5a0000h-5a7fffh ba186 32 kwords 598000h-59ffffh ba185 32 kwords 590000h-597fffh ba184 32 kwords 588000h-58ffffh ba183 32 kwords 580000h-587fffh - 47 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e bank block block size (x16) address range bank 10 ba182 32 kwords 578000h-57ffffh ba181 32 kwords 570000h-577fffh ba180 32 kwords 568000h-56ffffh ba179 32 kwords 560000h-567fffh ba178 32 kwords 558000h-55ffffh ba177 32 kwords 550000h-557fffh ba176 32 kwords 548000h-54ffffh ba175 32 kwords 540000h-547fffh ba174 32 kwords 538000h-53ffffh ba173 32 kwords 530000h-537fffh ba172 32 kwords 528000h-52ffffh ba171 32 kwords 520000h-527fffh ba170 32 kwords 518000h-51ffffh ba169 32 kwords 510000h-517fffh ba168 32 kwords 508000h-50ffffh ba167 32 kwords 500000h-507fffh bank 9 ba166 32 kwords 4f8000h-4fffffh ba165 32 kwords 4f0000h-4f7fffh ba164 32 kwords 4e8000h-4effffh ba163 32 kwords 4e0000h-4e7fffh ba162 32 kwords 4d8000h-4dffffh ba161 32 kwords 4d0000h-4d7fffh ba160 32 kwords 4c8000h-4cffffh ba159 32 kwords 4c0000h-4c7fffh ba158 32 kwords 4b8000h-4bffffh ba157 32 kwords 4b0000h-4b7fffh ba156 32 kwords 4a8000h-4affffh ba155 32 kwords 4a0000h-4a7fffh ba154 32 kwords 498000h-49ffffh ba153 32 kwords 490000h-497fffh ba152 32 kwords 488000h-48ffffh ba151 32 kwords 480000h-487fffh bank 8 ba150 32 kwords 478000h-47ffffh ba149 32 kwords 470000h-477fffh ba148 32 kwords 468000h-46ffffh ba147 32 kwords 460000h-467fffh ba146 32 kwords 458000h-45ffffh ba145 32 kwords 450000h-457fffh ba144 32 kwords 448000h-44ffffh ba143 32 kwords 440000h-447fffh ba142 32 kwords 438000h-43ffffh ba141 32 kwords 430000h-437fffh ba140 32 kwords 428000h-42ffffh ba139 32 kwords 420000h-427fffh ba138 32 kwords 418000h-41ffffh ba137 32 kwords 410000h-417fffh - 48 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e bank block block size (x16) address range bank 8 ba136 32 kwords 408000h-40ffffh ba135 32 kwords 400000h-407fffh bank 7 ba134 32 kwords 3f8000h-3fffffh ba133 32 kwords 3f0000h-3f7fffh ba132 32 kwords 3e8000h-3effffh ba131 32 kwords 3e0000h-3e7fffh ba130 32 kwords 3d8000h-3dffffh ba129 32 kwords 3d0000h-3d7fffh ba128 32 kwords 3c8000h-3cffffh ba127 32 kwords 3c0000h-3c7fffh ba126 32 kwords 3b8000h-3bffffh ba125 32 kwords 3b0000h-3b7fffh ba124 32 kwords 3a8000h-3affffh ba123 32 kwords 3a0000h-3a7fffh ba122 32 kwords 398000h-39ffffh ba121 32 kwords 390000h-397fffh ba120 32 kwords 388000h-38ffffh ba119 32 kwords 380000h-387fffh bank 6 ba118 32 kwords 378000h-37ffffh ba117 32 kwords 370000h-377fffh ba116 32 kwords 368000h-36ffffh ba115 32 kwords 360000h-367fffh ba114 32 kwords 358000h-35ffffh ba113 32 kwords 350000h-357fffh ba112 32 kwords 348000h-34ffffh ba111 32 kwords 340000h-347fffh ba110 32 kwords 338000h-33ffffh ba109 32 kwords 330000h-337fffh ba108 32 kwords 328000h-32ffffh ba107 32 kwords 320000h-327fffh ba106 32 kwords 318000h-31ffffh ba105 32 kwords 310000h-317fffh ba104 32 kwords 308000h-30ffffh ba103 32 kwords 300000h-307fffh bank 5 ba102 32 kwords 2f8000h-2fffffh ba101 32 kwords 2f0000h-2f7fffh ba100 32 kwords 2e8000h-2effffh ba99 32 kwords 2e0000h-2e7fffh ba98 32 kwords 2d8000h-2dffffh ba97 32 kwords 2d0000h-2d7fffh ba96 32 kwords 2c8000h-2cffffh ba95 32 kwords 2c0000h-2c7fffh ba94 32 kwords 2b8000h-2bffffh ba93 32 kwords 2b0000h-2b7fffh ba92 32 kwords 2a8000h-2affffh - 49 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e bank block block size (x16) address range bank 5 ba91 32 kwords 2a0000h-2a7fffh ba90 32 kwords 298000h-29ffffh ba89 32 kwords 290000h-297fffh ba88 32 kwords 288000h-28ffffh ba87 32 kwords 280000h-287fffh bank 4 ba86 32 kwords 278000h-27ffffh ba85 32 kwords 270000h-277fffh ba84 32 kwords 268000h-26ffffh ba83 32 kwords 260000h-267fffh ba82 32 kwords 258000h-25ffffh ba81 32 kwords 250000h-257fffh ba80 32 kwords 248000h-24ffffh ba79 32 kwords 240000h-247fffh ba78 32 kwords 238000h-23ffffh ba77 32 kwords 230000h-237fffh ba76 32 kwords 228000h-22ffffh ba75 32 kwords 220000h-227fffh ba74 32 kwords 218000h-21ffffh ba73 32 kwords 210000h-217fffh ba72 32 kwords 208000h-20ffffh ba71 32 kwords 200000h-207fffh bank 3 ba70 32 kwords 1f8000h-1fffffh ba69 32 kwords 1f0000h-1f7fffh ba68 32 kwords 1e8000h-1effffh ba67 32 kwords 1e0000h-1e7fffh ba66 32 kwords 1d8000h-1dffffh ba65 32 kwords 1d0000h-1d7fffh ba64 32 kwords 1c8000h-1cffffh ba63 32 kwords 1c0000h-1c7fffh ba62 32 kwords 1b8000h-1bffffh ba61 32 kwords 1b0000h-1b7fffh ba60 32 kwords 1a8000h-1affffh ba59 32 kwords 1a0000h-1a7fffh ba58 32 kwords 198000h-19ffffh ba57 32 kwords 190000h-197fffh ba56 32 kwords 188000h-18ffffh ba55 32 kwords 180000h-187fffh bank 2 ba54 32 kwords 178000h-17ffffh ba53 32 kwords 170000h-177fffh ba52 32 kwords 168000h-16ffffh ba51 32 kwords 160000h-167fffh ba50 32 kwords 158000h-15ffffh ba49 32 kwords 150000h-157fffh ba48 32 kwords 148000h-14ffffh ba47 32 kwords 140000h-147fffh - 50 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e bank block block size (x16) address range bank 2 ba46 32 kwords 138000h-13ffffh ba45 32 kwords 130000h-137fffh ba44 32 kwords 128000h-12ffffh ba43 32 kwords 120000h-127fffh ba42 32 kwords 118000h-11ffffh ba41 32 kwords 110000h-117fffh ba40 32 kwords 108000h-10ffffh ba39 32 kwords 100000h-107fffh bank 1 ba38 32 kwords 0f8000h-0fffffh ba37 32 kwords 0f0000h-0f7fffh ba36 32 kwords 0e8000h-0effffh ba35 32 kwords 0e0000h-0e7fffh ba34 32 kwords 0d8000h-0dffffh ba33 32 kwords 0d0000h-0d7fffh ba32 32 kwords 0c8000h-0cffffh ba31 32 kwords 0c0000h-0c7fffh ba30 32 kwords 0b8000h-0bffffh ba29 32 kwords 0b0000h-0b7fffh ba28 32 kwords 0a8000h-0affffh ba27 32 kwords 0a0000h-0a7fffh ba26 32 kwords 098000h-09ffffh ba25 32 kwords 090000h-097fffh ba24 32 kwords 088000h-08ffffh ba23 32 kwords 080000h-087fffh - 51 - k8a2815ebe-se7e datasheet nor flash memory rev. 1.0 K8A2815ETE-se7e [table 17] bottom boot block otp block addresses after entering otp block, any issued addresses should be in the range of otp block address bank block block size (x16) address range bank 0 ba22 32 kwords 078000h-07ffffh ba21 32 kwords 070000h-077fffh ba20 32 kwords 068000h-06ffffh ba19 32 kwords 060000h-067fffh ba18 32 kwords 058000h-05ffffh ba17 32 kwords 050000h-057fffh ba16 32 kwords 048000h-04ffffh ba15 32 kwords 040000h-047fffh ba14 32 kwords 038000h-03ffffh ba13 32 kwords 030000h-037fffh ba12 32 kwords 028000h-02ffffh ba11 32 kwords 020000h-027fffh ba10 32 kwords 018000h-01ffffh ba9 32 kwords 010000h-017fffh ba8 32 kwords 008000h-00ffffh ba7 4 kwords 007000h-007fffh ba6 4 kwords 006000h-006fffh ba5 4 kwords 005000h-005fffh ba4 4 kwords 004000h-004fffh ba3 4 kwords 003000h-003fffh ba2 4 kwords 002000h-002fffh ba1 4 kwords 001000h-001fffh ba0 4 kwords 000000h-000fffh otp block address a22 ~ a8 block size (x16) address range 0000h 256words 000000h-0000ffh |
Price & Availability of K8A2815ETE
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